MultiFrame Fast Search Motion Estimation and VLSI Architecture

This paper presents a fast Motion Estimation algorithm concept with reduction in execution time, which provides low power consumption in the design of hardware architecture. A new VLSI architecture for Integer Motion Estimation based on the Full search algorithm is proposed.This architecture uses Sum Of Absolute Difference (SAD) operation,the commonly used metric to determine the best match of the blocks. Computations and comparisons are performed using Carry Save Ahead Adder (CSA) and Carry Look Ahead Adder(CLA) for SAD operation. The design has been implemented on the Xilinx Spartran which depicts the characteristics of memory used , and power consumption. Fast search algorithm reduces search area by determining motion vectors for multiframes instead of single frame. The Motion Estimation algorithm is the most computationally intensive part of the encoder which is simulated using MATLAB.The proposed algorithm gives us a fast processing time schedule with a fixed number of computations. Multiframe motion estimation speeds up the computation time and the simulation results shows that PSNR value is high compared with the single frame process and computation time is reduced with negligible performance degradation.